1. Field of the Invention
This invention relates to a method for decreasing the resistivity of the gate and leaky junction of the source/drain, more particularly, to the method for forming a metal silicide layer at the gate region and the source/drain region by using two times in depositing metal layer. This condition will form a thicker metal silicide layer at the gate region to decrease the resistivity of the gate and will form a thinner metal silicide layer at the source/drain region to decrease defects in leaky junction at the source/drain region.
2. Description of the Prior Art
An increment in device integrity makes the resistance of metal oxide semiconductor (MOS) device source/drain regions gradually climb up and almost equal to the resistance of MOS device channel. In order to reduce the sheet resistance of source/drain regions and to guarantee a complete shallow junction between metal and MOS device, the application of a xe2x80x9cSelf aligned Silicidexe2x80x9d process is gradually steeping into the very large scale integration (VLSI) fabrication of 0.5 micron (xcexcm) and below. This particular process is called xe2x80x9cSalicidexe2x80x9d for short.
In general, the titanium silicon is usually used in silicide. The titanium silicide is formed to use two sequence steps rapid thermal process. At first, referring to FIG. 1, a silicon substrate 10 is provided and a MOS device and a shallow trench isolation are formed thereon. The MOS device comprises a source/drain region 12 a gate region, and as well as a spacer 18 formed on the sidewalls of the gate region. This gate region comprises a gate oxide layer 14 and a polysilicon layer 16, then using the chemical vapor deposition technique or the magnetron direct current sputtering technique to deposit a titanium the metal layer 20 over the MOS and the shallow trench isolation. The thickness of the titanium metal layer 20 is about more than 300 angstroms. Next, a rapid thermal process is performed, wherein part of the titanium metal layer will react with the silicon on the source/drain region and with the polysilicon of the gate region to form a titanium silicide layer. The thickness of this titanium silicide layer is about 600 to 700 angstroms. The structure of this titanium silicide layer is a metastable C-49 phase structure with higher resistivity. Referring to FIG. 2, the unreacted titanium metal and the remained titanium metal are removed by applying the RCA cleaning method. Therefore, the titanium silicide layer 22 is existed on top of the gate region and the source/drain region. Finally, a rapid thermal process is performed again to transformer higher resistivity of the C-49 phase titanium silicide structure into lower resistivity of the C-54 phase titanium silicide structure.
In the deep sub-micron device fabrication, the decline of the device driving current that cause by parasitic seties resistance of source/drain can be avoided by siliciding the source/drain. The above can be accomplished by either using simple silicidation of source/drain of self-aligned silicidation, where self-aligned silicidation can accomplish the silicidations of source/drain and gate region at the same time.
However, in accompanying with the shrinkage of the devices, the conventional method of depositing titanium metal to a thickness greater than about 300 angstroms, and as well as using rapid thermal process for forming titanium silicide, thicker silicon substrate is consumed at the source/drain region. Therefore, results in shallower junctions. In order to avoid the formation of leaky junctions, the thickness of the silicide layer at the source/drain region must be thinner enough as devices to be shrinked in size. If the thinner titanium metal layer is formed over the MOS and is passed through two times of the rapid thermal process, the produced titanium silicide layer is thinner at the source/drain region. But titanium silicide layer is following thinner at the gate region to cause higher resistivity of the gate. Therefore, the thicker titanium silicide layer is formed at the gate region and the thinner titanium silicide layer is formed at the source/drain region by using the present invention method.
In accordance with the above-mentioned invention backgrounds, the traditional method can not form a thicker metal silicide layer at the gate region and a thinner metal silicide layer at the source/drain region. The present invention provides a method to use two steps in forming metal layer to form a thicker metal silicide layer at the gate region and to form a thinner metal silicide layer at the source/drain region to decrease the volume of the semiconductor element successfully.
The second objective of this invention is to increase the integrity of the elements in the semiconductor by using two steps in forming metal layer to form a thicker metal silicide layer at the gate region and to form a thinner metal silicide layer at the source/drain region.
The third objective of this invention is to decrease the resistance value of the gate and decrease the defects in the leaky junctions of the source/drain region by using two steps in forming metal layer to form a thicker metal silicide layer at the gate region and to form a thinner metal silicide layer at the source/drain region.
It is a further objective of this invention to increase the qualities of the semiconductor elements by using two steps in forming metal layer to form a thicker metal silicide layer at the gate region and to form a thinner metal silicide layer at the source/drain region.
In according to the foregoing objective, the present invention provides a metal o use two steps in forming metal layer to form a thicker metal silicide layer at the gate region and to form a thinner metal silicide layer at the source/drain region to decrease the volume of the semiconductor element successfully and to increase the integrity of the elements in the semiconductor. When the volume of the semiconductor elements is decreased, the metal silicide at the gate region is thicker to cause the lower resistivity and the metal silicide at the source/drain region is thinner to cause the defects in the leaky junction hardly. Therefore, the qualities of the semiconductor elements can be increased by using the present invention method.